1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a split gate type nonvolatile memory device and a method of fabricating the same.
2. Description of the Related Art
Generally, semiconductor memory devices can be classified as volatile memory devices and nonvolatile memory devices. Stored data is lost in a volatile memory device when power is removed, whereas the nonvolatile memory device retains stored data even when power is removed. Therefore, nonvolatile memory devices are popular for certain applications where power conservation is of high priority, such as mobile phones, memory device cards for storing music and image data, and the like. Nonvolatile memory device types include a mask read-only memory (mask ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable EPROM (EEPROM), a flash memory device, etc. Among them, the flash memory device is popular since it offers the advantages of both the EPROM and EEPROM.
The flash memory device can generally be classified as a flash memory device with a stacked gate structure and a flash memory device with a split gate structure. Of the two, the flash memory device with the stacked gate structure has a problem in that data are erased excessively when erasing data, whereas the flash memory device with the split gate structure overcomes this problem.
FIG. 1 is a plane view of a conventional split gate type nonvolatile memory device, and FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1.
Referring to FIG. 1, an active region is defined on a semiconductor substrate I by an isolation region 2. A source region 3 and a drain region 4 are formed in the active region. Between the source and drain regions 3, 4, a floating gate 5 and a control gate 6 are formed. Herein, the source regions 3 are connected to each other in a predetermined direction so as to form a common source. The control gate 6 is formed to extend in parallel with the common source to constitute a word line. A vertical structure of the conventional split gate type nonvolatile memory device is illustrated in FIG. 2.
Referring to FIG. 2, the source region 3 and the drain region 4 are formed in the semiconductor substrate 1, and a channel is formed therebetween. A gate insulating layer 7 is formed on the semiconductor substrate 1, and the floating gate 5 is formed on a predetermined region of the gate insulating layer 7. A floating gate poly-insulating layer 8 is formed on the top surface of the floating gate 5 by a conventional local oxidation of silicon (LOCOS) method, and a tunneling insulating layer 9 is formed on one sidewall of the floating gate 5. The floating gate 5 is electrically isolated from the periphery by means of the gate insulating layer 7, the floating gate poly-insulating layer 8, and the tunneling insulating layer 9. Meanwhile, the control gate 6 is formed on the tunneling insulating layer 9 and the gate insulating layer 7, wherein the control gate 6 is disposed such that one end thereof overlaps the drain region 4, and the other end overlaps the floating gate 5.
Operation of the aforementioned nonvolatile memory device will now be briefly described. When performing a programming operation, a certain voltage is applied to the control gate 6 and the source region 3 so that channel hot electrons (CHE) penetrate from the substrate 1 through the gate insulating layer 7 and the CHE are accumulated at the floating gate 5. On the contrary, when performing an erase operation, a ground voltage is applied to both the drain region 4 and the source region 3, and a predetermined voltage is applied to the control gate 6. At this time, the electrons accumulated at the floating gate 5 penetrate through the tunneling insulating layer 9 by Fowler-Nordheim tunneling effect and they migrate into the control gate 6.
The operational characteristics with regard to the program and erase operations depend on the magnitude of the voltage coupled to the floating gate 5. As illustrated in FIG. 2, the floating gate 5, the control gate 6, and the floating gate poly-insulating layer 8 and the tunneling layer 9 interposed therebetween constitute capacitors. Likewise, the floating gate 5, the semiconductor substrate 1, and the gate insulating layer 7 interposed therebetween constitute a capacitor. As illustrated in FIG. 2, assuming that the capacitance of each capacitor to be C1, C2, C3 and C4, respectively, and the summation thereof to be Ct, i.e., Ct=C1+C2+C3+C4, a predetermined voltage, which is a ratio of C1 to Ct multiplied by the voltage applied to the source region 3 during the program operation, is applied to the floating gate 5. Therefore, as the capacitance C1 is high, the voltage applied to the floating gate 5 also becomes high so that it is possible to perform the program operation even in the case where a low voltage is applied to the source region 3. In order to increase the capacitance C1, the area of the region of overlap between the floating gate 5 and the source region should be large.
Likewise, in an erase operation, if the overlapping area between the floating gate 5 and the source region 3 is relatively large, the floating gate 5 can maintain a state of a low voltage as similar to the ground voltage applied to the source region 3 for the erase operation. In this case, it is possible to maintain a high voltage difference between the control gate 6 and the floating gate 5. Moreover, in this case, Fowler-Nordheim tunneling can easily occur from the floating gate 5 into the control gate 6.
As a result, it is preferable to increase the area of overlap between the floating gate 5 and the source region 3, in order to enhance the program/erase operational characteristics. However, as the overlapping area between the floating gate 5 and the source region 3 increases, the distance between the source region 3 and the drain region 4 becomes relatively short, which can induce problems such as the short channel effect or the like. Thus, for the split-gate type nonvolatile memory device, the amount to which the overlapping area between the floating gate 5 and the source region 3 can be increased is limited.